Title: Method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains
Type: issued patent
Patent number: 7,167,966
Issue date: January 23, 2007
Filing date: August 16, 2004
Link to PDF: 
AIPW Summary: A hardware-related patent that relates to calibrating time parameters between hardware elements based on how the system is actually performing. A clock signal generator is coupled to multiple hardware subsystems and supplies clock signals to each subsystem. The clock signal generator can supply a different clock signal to each subsystem, all of the clock signals being derived from a common clock, each clock signal having a different predetermined phase offset relative to the other clock signals. The phase offsets are adjustable based on the performance of the hardware subsystems. The patent describes various ways of determining performance of the hardware subsystems and when to adjust the clock phase offsets.